There are many types of packages used to manage the thermal, optical and electrical connections to small optoelectronic devices. This reason for this is the inherent conflict arising between thermal conductivity and electrical insulation when selecting suitable materials for packaging. Typical Optoelectronic devices include lasers, LEDs, detectors and photovoltaic devices. The largest challenges associated with the packaging come from electrically pumped light emitting devices. The conversion from electrical energy to light photons out dictates that the associated wall plug efficiency of the device is never unity, thereby introducing substantial heating in the vicinity of the small format device.
Of particular interest to the present invention are semiconductor light emitting diodes (LED) and lasers. These comprise of a chip level small format device and are typically driven at high drive currents resulting in high power densities generated inside the material causing local heating effects.
Light emitting diodes are based on a forward biased p-n junction. LEDs have recently reached high brightness levels that have allowed them to be used in new solid state lighting applications, as well as replacements for high brightness light sources, such as light engines for projectors and automotive car headlights. These markets have also been enabled by the economical gains achieved through the high efficiencies of LEDs, and also the reliability, long lifetime and environmental benefits. These gains have been partly achieved by use of LEDs that are capable of being driven at high currents and hence produce high luminous outputs while still maintaining high wall plug efficiencies.
The efficiency of the LED is critical to ensure that solid state lighting is adopted for general lighting applications and to provide an environmentally friendly lighting solution for future generations. LED lighting has the potential to be up to 20 times more efficient than the incandescent light bulb and to last 50-100 times longer (lasting up to 100,000 hrs), resulting in less physical waste, large energy savings and lower cost of ownership. Solid state lighting applications require that LEDs exceed efficiencies currently achievable by alternative fluorescent lighting technologies.
Current state of the art LED device performances have recently been demonstrated by Nichia Corporation, with a luminous efficacy figure of 161 lumen per Watt (LPW) being quoted for a white LED at an operating power of 61 mW. At the same time, both Nichia Corporation and Cree Inc. have recently achieved 134 lm/W and 129 lm/W, respectively, for high power LED devices at 350 mA current drive. The theoretical maximum is between 260 LPW and 330 LPW depending on the colour temperature of the white light generated. The present LPW efficacy at 1 W drive amounts to a wall plug efficiency (WPE) of 39.5%. Thus, greater than 60% of the electrical drive current is converted to heat. Typically, so called power chips are about 1 mm square and are driven between 1 W and 3 W. This amounts to a thermal load density of 0.6 to higher than 1.8 W/mm2. This is a high figure compared to any other semiconductor device, resulting in the need to provide specific high performance packaging solutions. To date, most packaging has been adapted from the IC industry, where thermal densities are orders of magnitude lower 1-3 W/cm2.
It is also of particular interest to maintain the small format light emitting device at a low temperature during operation, as the junction temperature of the LED dramatically affects both its life time and its overall efficiency. As a basic rule every 10° C. increase (above 25° C.) in junction temperature can reduce the life time of the LED by 10 kHrs for a Galium Nitride LED. It is also a consequence of the increase of the junction temperature that the overall efficiency of a state of the art vertical type LED drops. For example, increasing the junction temperature from 40° C. to a 70° C. will reduce the efficacy of the LEDs by more than 10%. It should noted that this effect is increasingly severe and nonlinear. Thus, appropriate packaging solutions need to be developed to ensure performance is maintained and the operating temperature of the light emitting device is maintained for a given change in the junction temperature as well as the ambient temperature.
The Thermal Resistance of a package is the measure of how well a package can conduct heat away from the junction of the LED. Current state of the art modules have a thermal resistance of between 4 and 15 K/W. Many methods have been successfully employed to improve the thermal resistance of LED module packages. These include the use of shaped metal lead frames in array formats, as described in U.S. Pat. No. 6,770,498, the use of bulk Aluminium Nitride ceramic tiles with electrical tracking on top, as described in published U.S Patent Application 2006/0091415A1, and the use of flip chip LEDs on tracked ceramic tiles with through vias to allow surface mounting, as described in published U.S Patent Application 2006/0091409A1.
The LEDs themselves have been engineered to produce a low thermal resistance path from the junction to the package where the heat is spread, such as the flip chip approach described above (U.S Patent Application 2006/0091409A1), in which the junction is very close to the package. In another approach to providing LEDs with high current and thermal driving capabilities, the vertical type n-p contact configuration in GaN material systems has been recently adopted. Examples of this have been disclosed in U.S. Pat. No. 6,884,646 and published U.S. Patent Application 20060154389A1. These documents describe the use of high thermal conductivity materials, such as Copper, to provide low thermal resistance from the junction to the package. More recently, improvements to these vertical type LED designs with respect to optical extraction performance promise even greater wall plug efficiency chips as described in UK patent applications 0704120.5 and 0714139.3.
We now review Insulated Metal Core Printed Circuit Boards, as their use is common place. Insulated metal substrate printed circuit boards (IMS-PCB) are described in U.S. Pat. No. 4,810,563. These are use in many applications including power electronics and LED packaging. The structure of devices using this approach is shown in FIG. 1.
The metal substrate 100 is commonly Aluminium or copper and ranges in thickness between 0.5 mm to 3.2 mm. On top of the substrate is an adhesive layer 101 typically consisting of particulate loaded epoxy. The particulates are chosen to increase the thermal conductivity and include Aluminium Nitride, Diamond and Beryllium Nitride. The choice of materials for the adhesive layer 101 is important as the IMS PCB will undergo solder operations with temperatures used during reflow being as high at 320° C.
Layer 102 is a polyamide film. On top of layer 102 is layer 103 an electrical circuit layer than usually consists of copper. Layer 103 has two functions. One is heat spreading and the other is to provide the electrical circuit layout for the application. On top of this layer is an insulator layer 104 to prevent surface short circuits and corrosion.
Typically, to get the required electrical isolation of kilovolts using a polyamide material (layer 102), a 75 micron thick sheet is needed. For this, the thermal conductivity is only 2.2 W/(m·k). This level is adequate for power electronics where thermal load densities are of the order of Watts/square-cm and a significant improvement in performance over FR4 circuit boards. However, if this type of IMS-PCB is used with the LED placed directly on the PCB, then high junction temperatures will occur, as the thermal load will not be able to spread adequately in layer 103.
The IMS-PCB is widely used in the LED packaging industry, as it can be used to mount ceramic packages, which perform the function of heat spreading and thus make the thermal load equivalent to that of power electronics. In addition to this advantage, the IMS-PCB can be machined with holes to allow mechanical attachment to a heat sink.
Of course, all these layers of packaging create extra cost and extra interfaces that increase thermal resistance. The best LEDs packaged in ceramic modules on IMS-PCBs provide a thermal resistance of about 10-15 K/W from the junction to the base of the module. An LED packaged in this way is shown in FIG. 2. The metal substrate 201 has the adhesive layer 202 attaching a polyamide electrical insulation layer 203. On top of this is the metal circuit tracking layer 204. This assembly comprising layers 201, 202, 203 and 204 is the IMS-PCB 221. On top of this is soldered or bonded, using layer 205, the electrically insulating but thermally conducting ceramic tile (214), with the LED (212) attached by a solder or adhesive layer 213. The ceramic tile, 214, can be formed from any number of ceramics, such as alumina or aluminium nitride. The top electrical connection from the LED (212) to the electrical circuit layer 208 on the top of the ceramic tile (214) is via a wire bond 211. The electrical circuit layer 208 is in electrical contact with the bottom electrical circuit layer 206 through the use of an electrical via 207. The bottom electrical contact of the LED 212 is in electrical contact with the top electrical contact 215 of the ceramic tile through the use of a solder joint 213. This in turn is in electrical contact with the bottom side (217) of the ceramic tile 214 through the use of additional electrical via or vias 216.
The use of the thermally conductive ceramic tile 214 ensures that the large bottom contact 220 acts as the thermal path to the IMS PCB 221, but there is no electrical connection as no electrical vias are used in this section of the ceramic title 214. Thus, the top electrical contact to the LED and the bottom electrical contact to the LED are separated through the used of the IMS PCB 221, and any heat sink attached to the bottom side of the IMS PCB 221 is electrically isolated. This is an important issue, if typical metal, graphite or conductive plastic heat sinks are used to prevent the heat sink becoming electrically live. The LED 212 is encapsulated with a non conducting epoxy or silicone encapsulant 210, held in a cup or receptacle 209 to allow good light extraction. Lenses are often used in addition, although this is not depicted as this is not the focus of the present invention. The use of a ceramic tile allows for smooth surface on which to attach the LED. With LED solder joints being as thin as 3 um (gold tin solders), the surface morphology of the ceramic tile this is an important factor.
By cutting into the metal core of the IMS PCB and soldering a ceramic tile in direct contact with the core of the board, the thermal resistance can be reduced. The best LEDs of the prior art, which are packaged using Aluminium Nitride ceramic tiles soldered into the core of the IMS PCB, offer thermal resistance of 4 K/W from the LED junction to the base of the modules.
An LED packaged in this way is shown in FIG. 3. The metal substrate 301 has an adhesive layer 302 attaching a polyamide electrical insulation layer 303. On top of this is the metal circuit tracking layer 304. This assembly comprising layers 301, 302, 303 and 304 is the IMS-PCB 316. The electrical tracking of the IMS-PCB 316 and the electrical circuit layer 306 of the ceramic tile 317 are electrically connected to together through the use of wire bonds 305. The ceramic tile, 317, can be any number of ceramics such as alumina or aluminium nitride, although aluminium nitride is preferred due to its high thermal conductivity. The top electrical connection from the LED (309) to the electrical circuit layer 306 on the top of the ceramic tile (317) is via a wire bond 307. The bottom electrical contact of the LED 309 is in electrical contact with the top electrical contact 312 of the ceramic tile through the use of a solder joint 308.
The use of the thermally conductive ceramic tile 317 ensures that there is a low resistance thermal path to the metal substrate 301. Thus, the top electrical contact to the LED and the bottom electrical contact to the LED are separated through the used of the IMS PCB 316, and any heat sink attached to the bottom side of the IMS PCB 316 is electrically isolated through the use of the ceramic tile 317. This is an important issue if typical metal, graphite or conductive plastic heat sinks are used to prevent the heat sink becoming electrically live. The LED 309 is encapsulated with a suitable encapsulant such non-conducting epoxy or silicone encapsulant 310, held in a cup or receptacle 311 to allow good light extraction. Lenses are often used in addition, although this is not depicted as this is not the focus of the present invention.
A recent paper by K C Chen et al at the Electronic Components and Technology Conference 2007 describes how electroplating of standard LEDs on sapphire substrates can be used to remove solder joints and form the LED submount directly on the sapphire substrate (coated with a seed layer of metal to permit the electroplating). This arrangement is shown in FIG. 4.
The LED 412 consists of a sapphire substrate 402 thinned to 100 microns and upon which has been grown a layer of n-doped semiconductor such as Gallium Nitride. The electrical contact and wire bond pad 409 is in contact with this n-doped semiconductor and forms the n contact to the p-n junction 404. The p-type semiconductor 405 is in contact with the top transparent contact layer 406, which in turn is in contact with the metal wire bond pad 407. A thin layer of metal 401 is deposited or evaporated onto the sapphire substrate 402. This metal layer forms the seed layer for subsequent electroplating. The LED 412 is embedded in the copper plate 400 via electroplating. The electroplating can produce any thickness of copper plate given sufficient time in the plating solution.
The wire bonds 408 and 410 provide electrical paths from the p-contact 407 and the n-contact 409 to a conductive wirebondable layer 411 on an insulator 413. Thus, the electrical paths are insulated from the copper plate 400. The lateral chip 412 has a sapphire substrate 402, which provides electrical isolation between the thermal path and the package 400. This is a desirable feature, as it permits simplification of the packaging, thereby allowing the module to be mounted directly on a electrically and thermally conducting material such as a heat-sink without it being electrically live. This is particularly important when high DC or AC voltages are present and for safety reasons in the event of driver failure or short circuit.
The thermal performance of this kind of LED grown on a sapphire wafer is poor, as the thermal conductivity of sapphire is low at 40 W/(m K) and the wafer is typically quite thick at 100 microns, thus creating a large thermal resistance path as high as 2.6 K/W. Many manufactures thin the wafer after processing to minimise the thermal resistance. Nevertheless, these type of chips show a drop in efficiency, when driven hard (>0.5 W electrical drive power), due to elevated p-n junction temperatures associated with heat build up in the chip. Another issue for this kind of device is that of current crowding around the contacts 409 and 407, with associated below optimum current injection into areas not near the p and n contacts further reducing efficiency. In addition, the light extraction can be quite poor due to trapped modes in the sapphire substrate 402.
In the LED device 412 of the prior art, both n and p contacts are pressed into a soft polymer on a glass sheet. The 3 mm copper submount is then electroplated onto the back of the chip and the glass sheet and polymer then removed by dissolving the polymer. The sapphire is 100 microns thick and thus the thermal resistance of this part of the LED package is still relatively high. This thinning of sapphire is common commercial practice. Typically, the sapphire is thinned from 400 micron to 100 microns thick or so, depending on the wafer size post the growth of the LED by MOCVD or MBE. However, thinning the sapphire less than 100 microns causes the 2 inch or larger sapphire wafers to become extremely fragile during processing.